This year’s IEEE Electronic Components and Technology Conference (ECTC) saw a series of workshops on heterogeneous integration and a nice overview of the current state (2019 revision) of the Heterogeneous Integration Roadmap. The advent of SoMs/CoMs, and a plethora of SoCs in specialty applications like smartphones, all illustrate how integration is playing a role in increasing the functionality of chips without significantly increasing their footprint. Integration initiatives in the electronics were originally developed with a single goal: drive more features into smaller spaces and continue scaling devices without increasing footprints.

Heterogeneous integration plays into the larger theme that has been seen with ASICs over the last decade but takes it to a new level with advanced packaging technologies. If you’re a PCB designer or a systems designer, how will more highly integrated components affect your designs and layout practices? We can already look to some of today’s advanced GPU and CPU products for use in data center servers and mil-aero embedded computing for some guidance. However, these products will inevitably filter down to the everyday designer as technologies like embedded AI, quantum, 5G/6G, advanced robotics, and mixed functionality systems become more commonplace.

Integration in the Semiconductor Industry

The Semiconductor Industry Association (SIA) recently announced it would stop pursuing the activities outlined in the International Technology Roadmap for Semiconductors (ITRS) in the spring of 2016. Before that, the US segment of the industry followed its own National Technology Roadmap for Semiconductors (NTRS) until international companies began joining in the late 1990s. The move away from the ITRS and into a new paradigm for integration is a major shift, especially when you hear so much about the dominance of Moore’s Law in driving semiconductor scaling. Today, everyone in the industry accepts that continued scaling under Moore’s Law is producing diminishing returns for all except major companies like Intel and TSMC.

After the ITRS came the International Roadmap for Devices and Systems, a subset of which is the Heterogeneous Integration Roadmap. In today’s era of IoT, cloud-connected data centers, and smart devices, this technology roadmap takes the focus away from physical scaling of transistor-based circuits, something which drove the industry up to the current sub-7 nm node. Now the focus is on new architectures with an application-driven roadmap to enable a host of new applications. When you consider that the point of heterogeneous integration is to pack diverse features into a single package, what’s left for the board designer to do?

As it turns out, there is plenty left for board designers, and in fact, they will function as the primary interface between the real world and a black box component. First, let’s look at what is heterogeneous integration, and we’ll see how the role of the PCB designer will continue to shift away from basic layout tasks to systems design and integration at the board level.

What is Heterogeneous Integration?

Very simply, heterogeneous integration is the integration of multiple components, which may be separately manufactured, into a true system in package (SiP), where a single assembly provides all functionality by connecting all the constituent components. Think of an SoC but with more silicon dies; each component is fabricated separately and linked together with a standard interconnect structure.

To see what this means, let’s look at how we get to a heterogeneously integrated component. Consider the example below: we have multiple semiconductor dies from different fabs, and possibly produced with different technologies at different nodes. These are integrated into a single interposer and interconnected using standard methods (vias and tracks). Any of these modular dies could be connected together like legos with standardized interfaces.

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Simplified idea in heterogeneous integration

In some ways, this mimics the push to develop ASICs from the 1970s until today, where functions that would have been quite difficult to deal with using general purpose programmable logic or discrete components were implemented with a single specialized chip. Now, most of the boards you’ll build for specific applications involve a range of ASICs, some power regulation components, a bunch of passives, a processor, and maybe some specialty logic components. If you’re building a board that needs an analog front-end or must capture some analog signal from another instrument, that block will either be built into your ASIC, or there will be some interface IC (e.g., an ADC) that you can put onto the board for that function.

Current Single-chip Module Structure

For the designer who doesn’t necessarily follow developments in semiconductor packaging, I’ve shown an example of some integration methods and an example SoC below. The top-left image shows a typical BGA package where the Si die is encased in a mold compound. The other two images on the top row show how multiple dies can be stacked and interconnected to each other or to the BGA footprint with bond wires. Finally, the lower image shows the most sophisticated form of heterogeneous integration, where memory and logic sections are integrated into a single package using vias, known as through-silicon via (TSV) technology.

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Heterogeneous integration examples.

Why is there a focus on building out larger packages from a set of smaller chips? In planar semiconductor manufacturing processes, yield is lower when the die is thicker, so building out a very large-scale module in 3D becomes less economical when more features are packed onto a single die. Using separate dies that are interlinked with a standard interconnect architecture is more reliable. It also allows chip designers to take a modular approach to developing chip assemblies, where multiple dies can fit together like legos. You can then extend this to multi-chip assemblies, where multiples of the above die structure are linked together into a single package. This has been recently used in AMD’s Fiji and Epyc processors, and it is one method for bringing multiple cores into a single chip.

In terms of components and capabilities, most of the focus in heterogeneous integration is on packaging different digital components into a larger assembly, although analog and electromechanical components (e.g., MEMS) are also target constituents for heterogeneous integration. If it can be manufactured on a wafer with a planar process, then it’s a possible target for heterogeneous integration. This potential for integration among disparate capabilities leads us to the various areas that have received focus in the Heterogeneous Integration Roadmap.

Focus Areas in the Heterogeneous Integration Roadmap

The Heterogeneous Integration Roadmap was published in 2019 to address the challenges inhibiting further integration in specific application areas. This document is sponsored by three IEEE societies that reflect the current and future states of the electronics ecosystem. The Heterogeneous Integration Roadmap is distinguished from other standards roadmaps in that it is application and challenge focused, rather than being focused on specific capabilities. There are six chapters outlined in the Heterogeneous Integration Roadmap focusing on technical challenges in specific areas:

  • High-performance computing and data centers, which are natural targets for continued miniaturization and integration

  • Mobile devices, including 5G and future mobile networking capabilities like 6G

  • Automotive, addressing primarily autonomous vehicles

  • Medical/health devices and wearables, which often require a range of components providing specialized functions

  • Aerospace and defense, another area where a multitude of functions are implemented in physically large systems for specialty applications

  • IoT, a category broad enough to overlap with any of the above areas

Going deeper, the Heterogeneous Integration Roadmap addresses technical challenges and potential solutions for some broad groups of components. Some of these component groups are common in many systems, and today are implemented with multiple circuits or component sets:

  • Single-chip and multi-chip modules

  • Integrated power electronics

  • Integrated sensor platforms, including MEMS sensors

  • Integrated photonics

  • 5G chipsets

Different Levels of Heterogeneous Integration

The trend here is one of packing more computing power and additional features into standard packages, but with a focus at 3 levels:

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Each of these levels of heterogeneous integration aims to address different technical challenges.

Chip Heterogeneity

Chip heterogeneity is focused on feature-level integration by integrating multiple chips into a single package. This follows closely the design of chiplets and multi-chip modules. Some examples of hardware integration at this level include:

  • Mixing different package styles in the same module

  • Stacking of multiple chips vertically and horizontally (2.5D/3D integration)

  • Packing multiple SoC modules into a larger module

All this is linked together with wafer-level packaging technologies, such as TSV for vertical integration and TSMC’s integrated fan-out (InFO) used in wireless SiPs. Interconnect techniques that don’t rely on bond wires are highly desired, especially for ultra-high speed serial data streams passing between dies.

System Heterogeneity

Different products are more ideal for processing different data structures, and system-level integration aims to address tasks where computational workloads are passed between different modules. For example, repetitive vector calculations are best performed on GPUs, while matrix calculations used in AI models are now being performed on ASICs. SiPs need to have these options available alongside interfaces, memories, processor cores, and I/O interfaces to provide the most computationally efficient processing for specific workloads.

This level of heterogeneous integration is more suited for data centers, where multiple data workloads (scalar, vector, matrix, and spatial) need to be processed simultaneously. However, this can certainly be extended to embedded applications involving RF/wireless, as well as photonics components.

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Example SiP for autonomous vehicle applications with integrated photonics circuitry. [Source]

Firmware/Software Homogeneity

This is a major challenge as it requires significant standardization across a set of products in terms of embedded operating systems and a set of standard APIs. This is more difficult because developers generally use different languages and with different areas of specialization. We’ll likely continue to have many high-level languages for developing applications that will run and interface with heterogeneous modules. However, what developers need is a single development environment that compiles code from multiple languages into a single codebase. It’s still unclear what this type of environment will look like, but chipmakers are working towards this type of development environment to support heterogeneous products.

What Heterogeneous Integration Means for PCB Designers

For PCB designers, this trend of greater integration packs more functions and features onto a single chip and gives designers more specialized products for different applications. Designers working in upcoming areas of technology will spend less time fitting together groups of disparate components as standardized products will contain the required features in a single device. PCB designers will still have layout challenges to contend with, but heterogeneous integration helps reduce overall component count, system size, and required peripherals without changing layout practices for PCB designers.

Does this mean PCB designers will just be wiring up a power block and a heterogeneously integrated module on the board? Of course not... the Heterogeneous Integration Roadmap is applications-based and meant to drive production of components that target broad application areas. By focusing on broad application areas, new products will consolidate components for specific chipsets into a single module, and standard interfaces (PCIe, USB, etc.) would be used to link modules together.